1. Field of the Invention
This invention relates to wafer processing in the integrated circuit fabrication. More particularly, this invention relates to an improved method to form self-aligned silicide layers on an integrated circuit structure.
2. Description of the Prior Art
In today's integrated circuit fabrication, heavily doped diffusion strips (N+ source and drain" hereafter called S/D" in NMOS process and P+ S/D in PMOS process) and heavily doped polycrystalline silicon (hereafter called poly) lines are used for the electrical interconnections. With the continuously scaling down dimensions of semiconductor devices, the S/D resistance of the transistor and the poly-line resistance become more critical for the better performance of devices in integrated circuits. One method to reduce the resistance is to form silicide layers on S/D areas and on poly lines. The simplest technique was to form self-aligned silicide layers right after the formation of S/D junctions. But this method easily resulted in the electrical short between S/D and the polygate of the transistor. In order to prevent the electrical short, oxide spacers 5 were employed as shown in FIG. 1. After the formation of N+ S/D 4 junctions by employing implantation method with the use of the poly-gate 3 on the gate-oxide 2 as implant mask (P-type substrate 1 was used as an example for NMOS process), CVD (Chemical Vapour Deposition) oxide was deposited and anisotropically etched to form oxide spacers 5 on sidewalls of the poly-gate 3. The anisotropical oxide etch could be achieved with the dry etch technique which was commonly employed in the contact via etch the integrated circuits fabrication. Then, the transition metal layer 6 was sputter-deposited to the desired thickness. The transition metal can be selected from the group of Ti, W, Mo, Pt, Pd, Ni, or Ta etc., depending on the requirements of the process. After the sputter of the transition metal layer 6, silicide was formed by annealing at elevated temperature in a fuenace tube so that silicon and transition metal could react wherever they had intimate contact until total transition metal on silicon surfaces of S/D 4 and Poly-gate 3 had reacted with silicon to form silicide layer (not shown in FIG. 1). After the silicide formation, the unreacted transition metal was selectively etched (not shown in FIG. 1), for example, with the solution consisting of NH4OH, H2O2, and H2O. This technique suffers several drawbacks. For example, silicide can be formed on the surface of the oxide spacer 5 because of the lateral silicide growth. Also transition metal like Ti can react with oxide to form TiO2 which can not be selectively removed. In order to overcome these difficulties, the two-step anneal process was developed (for example see "novel submicrometer MOS devices by self-aligned nitridation of cilicide" by Haneko et al, IEEE Tran. Elec. Dev., ED-33, p. 1702, 1986). In this process, silicide was first formed at relatively low temperature in the furnace tube (just high enough to stimulate the reaction between silicon and transition metal) after the sputtered deposition of the transition metal layer 6. At this low temperature, there is little reaction between transition metal and oxide. Then, the selective etch was carried out to removed the unreacted transition metal on surfaces of oxide spacers 5. Finally, high temperature anneal step was carried out in the furnace tube to achieve the final low value of the resistance. This two-step anneal process still suffers many difficulties including (1) Although the lateral silicide growth is reduced, it is not eliminated. The lateral silicide growth is determined by the first low temperature anneal step. Therefore, this low temperature anneal step is very critical, (2) It is difficult to form silicide layer with varying thicknesses. Since it is required that poly interconnect line have thicker silicide layer to lower the resistance, while it is required that the transistor's source and drain have thinner silicide layer in order not to penetrate the shallow S/D junctions, (3) Because of the lateral silicide growth, the pre-patterned poly lines will change dimensions when the thicker silicide layer is formed to achieve lower resistance. This invention will teach a technique to overcome these difficulties and provide a simple and less critical process to form self-aligned silicide layers.